Functional Blocks: FHDL

Sample: circuit

inputs InputA,LoadA,InputB,LoadB,ALUControl,LoadC,Clock

outputs OutputC

RegA: register (InputA,LoadA,Clock),(ALULeft),clock=yes

wire InputA,width=32

wire ALULeft,width=32

RegB: register (InputB,LoadB,Clock),(ALURight),clock=yes

wire InputB,width=32

wire ALURight,width=32

MainALU: alu (ALULeft,ALURight,ALUControl),(InputC),

control=(carryin,cenable),

function=(0,and,4,or,8,xor)

wire ALUControl,width=6

RegC: register (InputC,LoadC,Clock),(OutputC),clock=yes

wire InputC,width=32

wire OutputC,width=32

endcircuit