Hierarchical FHDL

HalfAdder: circuit

Inputs A,B

Outputs S,C

G1: xor (A,B),S

G2: and (A,B),C

endcircuit

FullAdder: circuit

Inputs A,B,C

Outputs Sum,Carry

SS1: HalfAdder (A,B),(S1,C1)

SS2: HalfAdder (C,S1),(Sum,C2)

G3: or (C1,C2),Carry

endcircuit

FourBit: circuit

Inputs A4,A3,A2,A1,B4,B3,B2,B1,C0

Outputs S4,S3,S2,S1,C4

SS1: FullAdder (A1,B1,C0),(S1,C1)

SS2: FullAdder (A2,B2,C1),(S2,C2)

SS3: FullAdder (A3,B3,C2),(S3,C3)

SS4: FullAdder (A4,B4,C3),(S4,C4)

endcircuit