We have a number of technical reports that describe FHDL, its implementation, and other research in logic simulation.
These technical reports are in adobe acrobat format.
Click here to view the abstracts.
Click on the report number to view the report.
| Number | Title |
| DA-1 1991 | GATEWAYS: A TECHNIQUE FOR ADDING EVENT-DRIVEN
BEHAVIOR TO COMPILED UNIT-DELAY SIMULATIONS |
| DA-2 1990 | DYNAMIC FUNCTIONAL TESTING FOR VLSI CIRCUITS |
| DA-3 1989 | THE FLORIDA HARDWARE DESIGN LANGUAGE |
| DA-4 1991 | USING GATEWAYS WITH LEVELIZED COMPILED SIMULATION |
| DA-5 1989 | HDL DRIVEN CHIP LAYOUT WITHIN THE FHDL DESIGN FRAMEWORK |
| DA-6 1990 | MDCSIM: A COMPILED EVENT-DRIVEN MULTI-DELAY SIMULATOR |
| DA-7 1991 | TWO NEW TECHNIQUES FOR COMPILED MULTI-DELAY SIMULATION |
| DA-8 1989 | TECHNIQUES FOR MULTI-LEVEL COMPILED SIMULATION |
| DA-9 1990 | OPTIMIZATION OF THE PARALLEL TECHNIQUE FOR COMPILED UNIT-DELAY SIMULATION |
| DA-10 1990 | AUTOMATIC ROUTING OF INTEGRATED CIRCUIT CONNECTIONS: A TUTORIAL |
| DA-11 1991 | THE SHADOW ALGORITHM: A SCHEDULING TECHNIQUE FOR BOTH COMPILED AND INTERPRETED SIMULATION |
| DA-12 1988 | SCHEDULING HIGH-LEVEL BLOCKS FOR FUNCTIONAL SIMULATION |
| DA-13 1988 | THE COMPLEXITY OF DETECTING SYMMETRIC FUNCTIONS |
| DA-14 1991 | COMPILED UNIT-DELAY SIMULATION FOR CYCLIC CIRCUITS |
| DA-15 1989 | TECHNIQUES FOR UNIT-DELAY COMPILED SIMULATION |
| DA-16 1991 | TWO NEW TECHNIQUES FOR UNIT-DELAY COMPILED SIMULATION |
| DA-17 1990 | COMPILED UNIT-DELAY SIMULATION FOR CYCLIC CIRCUITS |
| DA-18 1989 | THE FHDL MACRO PROCESSOR |
| DA-19 1988 | COSIM: AN EXPERIMENTAL CONCURRENT FAULT SIMULATOR |
| DA-20 1989 | LECSIM: A LEVELIZED EVENT DRIVEN COMPILED LOGIC SIMULATOR |
| DA-21 1989 | THE FHDL PLA TOOLS |
| DA-22 1989 | THE FHDL ROM TOOLS |
| DA-23 1991 | SCHEDULING BLOCKS FOR HIERARCHICAL COMPILED SIMULATION |
| DA-24 1995 | IS COMPILED SIMULATION REALLY FASTER THAN INTERPRETED SIMULATION? |
| DA-25 1995 | THE INVERSION ALGORITHM FOR DIGITAL SIMULATION |
| DA-26 1995 | PARALLEL MULTI-DELAY SIMULATION |
| DA-27 1995 | THREE-VALUED SIMULATION WITH THE INVERSION ALGORITHM |
| DA-28 1995 | UNIT DELAY SCHEDULING FOR THE INVERSION ALGORITHM |
| DA-29 1995 | FANOUT FREE BLOCKS AND MULTI-DELAY LOGIC SIMULATION |
| DA-30 1995 | MDCSIM: A COMPILED EVENT-DRIVEN MULTI-DELAY SIMULATOR |
| DA-31 1995 | THE FHDL MANUAL |
| CA-1 1995 | SAM: A Multithreaded Pipeline Architecture for Dataflow Computing |
| CA-2 1995 | Strategies for Implementing a Multithreaded Shared Pipeline Processor |
| CA-3 1995 | A Multithreading Architecture with Multiple Independent Shared Pipelines |
| CA-4 1995 | MAPPING THE DATA FLOW MODEL OF COMPUTATION INTO AN ENHANCED VON NEUMANN PROCESSOR |
| CA-5 1995 | Appendix A. A Sample program for Matrix Multiplication |
| SE-1 1991 | THE DESIGN AND IMPLEMENTATION OF A GRAMMAR-BASED DATA GENERATOR |
| SE-2 1990 | Generating Test Data with Enhanced Context Free Grammars |
| SE-3 1995 | THE DGL MANUAL |